Nonvolatile memory devices generally include an array of MOS transistors, or “cells,” having specialized gate structures that are designed to retain digital values, even in the absence of power to the device, by trapping or storing charge. Electronically erasable programmable read-only (EEPROM) memory devices and flash EEPROM devices (“flash”) are two examples of nonvolatile memory devices. The term “EEPROM” is sometimes used to refer to devices that are generally programmable and erasable at a byte level, and “flash memory” is sometimes used to refer to devices that are generally programmable and erasable in sections larger than one byte.
The memory cells in a flash device are generally arranged in blocks referred to as “pages.” Each page may store many bytes of data. For example, a 256 kilobyte (K) flash device may be arranged as 1024 pages where each page stores 256 bytes of data. As another example, a 256K flash device may be arranged as 512 pages, where each page stores 512 bytes of data. Bytes within a page may be individually addressable, or they may be organized as larger words (e.g., 2-byte words, 4-byte words, etc.) The memory cells in a flash device are generally programmed or erased at the page level. That is, data in an entire page may be erased simultaneously, rather than in a byte-by-byte manner. Similarly, an entire page of flash may be programmed simultaneously through the use of a volatile page buffer.
The volatile page buffer generally has the same capacity as an individual page of nonvolatile flash memory. For example, a flash device that is arranged in 256-byte pages will generally have a 256-byte page buffer. To write data to a flash device, the data may be first written to the page buffer. When the page buffer is filled and a page of flash memory specified, the entire page buffer may be written to the specified page of flash memory. The page buffer may then be erased, refilled and written to another page of flash memory. Because flash memory is generally written one page at a time, data should be written in a manner that is compatible with the internal page structure (number of pages, bytes per page, and word size) of the flash memory.
During fabrication of flash memory, charge may accumulate within individual memory cells. To initially configure a flash memory device for use, the flash memory device may be subjected to a configuration process to dissipate the accumulated charge and “reset” each cell of the flash memory device to an initial, predictable state, where both ‘0’ and ‘1’ logic values may be written and read back with sufficient internal voltage margins between the values. One method of initially configuring a flash memory device is to alternately erase and write a pattern to each page in the flash memory device. This sequence may be repeated a number of times.
Flash memory may be included in a stand-alone memory chip, or it may be embedded in a chip that provides functions beyond just storing data. For example, flash memory may be included in a microcontroller having a processing unit, registers, embedded memory, peripherals and various interface ports. Either a stand-alone flash memory chip or a device having embedded flash memory ma y be part of a larger circuit that includes, for example, a printed circuit board (PCB) and various other electrical components. A flash memory array may also be included in a package with other modules that make up a “system on a chip” (SOC).
At either a PCB level or at a die level, various components, including flash memory, may be tested or configured following the fabrication process. Testing or configuring a PCB or a die may include direct electrical stimulation of various pins on a device or connections (“nets”) on a die to verify connectivity or functionality. Testing or configuration of a PCB or die may also include the use of specialized circuitry. For example, components of portions of a die may be tested or configured using a boundary scan testing protocol such as a protocol developed by the Joint Test Action Group (JTAG) and described in IEEE Standards 1149.1 and 1149.1A.
To facilitate boundary scan testing and configuration using boundary scan resources, portions of a die or various components on a PCB may be accessible from and serially connected to a Test Access Port (TAP), which may relay certain serial signals used by a boundary scan protocol. The signals may include for example, a clock signal, a mode signal, a serial input and a serial output (e.g., “TCLK,” “TMS,” “TDI” and “TDO”). By serially shifting in test command or configuration data via the mode signal, and serially shifting in test patterns or programming data via the serial input, an appropriate boundary scanning protocol may facilitate tests of connectivity between components, integrity of nets on a die, or certain functionality; or the boundary scan protocol may configure memory or some other configurable device.